Semiconductor integrated circuit and system

ABSTRACT

A semiconductor integrated circuit  10  includes a semiconductor substrate  1,  an insulating layer  2  formed on the semiconductor substrate  1,  and a bonding pad  3  formed on the insulating layer  2.  The semiconductor substrate  1  has a region  4  facing the bonding pad  3  and a region  5  substantially surrounding at least a part of the region  4.  The region  5  of the semiconductor substrate  1  is set substantially at an equipotential.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor integratedcircuit and system for reducing a power loss and noise caused by aparasitic element of a bonding pad, and specifically a semiconductorintegrated circuit and system having a pad structure suitable forinputting and outputting a signal having a high frequency.

BACKGROUND ART

[0002] In the field of computers, the clock frequency has been increasedin order to operate the computers at a higher speed. This requiresmemories and other peripheral devices to input and output a signalhaving a higher frequency in order to realize a higher speed interface.

[0003] Communication systems are also required to have a capability ofinputting and outputting a signal having a higher frequency at a lowerpower loss and lower noise. For example, digital cell phones such as PHSphones use a signal having a frequency of 1 GHz to 2 GHz. Accordingly,it is required to transmit and receive such a signal at a lower powerloss and with lower noise.

[0004]FIG. 20 shows a structure of a conventional communication system200. The communication system 200 includes an RF section 210 fortransmitting or receiving a signal and a baseband signal processingsection 220 for processing a signal to be transmitted or a signalreceived. Conventionally, the RF section 210 and the baseband signalprocessing section 220 are formed on different chips. For example, theRF section 210 is formed on a GaAs substrate, and the baseband signalprocessing section 220 is formed on a silicon substrate.

[0005] A signal received by an antenna 201 is input to a low noiseamplifier (LNA) 211 of the RF section 210 through atransmitting/receiving switch 202. The LNA 211 amplifies the receivedsignal. The amplified signal is input to a mixer 213 though a filter212. The mixer 213 mixes the signal output from the filter 212 and anoscillation signal output from an oscillator 214. The output from themixer 213 is supplied to the baseband signal processing section 220.

[0006] The baseband signal processing section 220 includes a converter221 and a digital signal processor (DSP) 222. The converter 221 convertsthe analog signal output from the mixer 213 into a digital signal. TheDSP 222 processes the digital signal.

[0007] The digital signal processed by the DSP 222 is converted into ananalog signal by the converter 221. A mixer 215 of the RF section 210mixes the signal output from the converter 221 and an oscillation signaloutput from the oscillator 214. A power amplifier (PA) 216 amplifies theoutput from the mixer 215. The amplified signal is transmitted from theantenna 201 through the transmitting/receiving switch 202.

[0008]FIG. 21 schematically shows an equivalent circuit from the antenna201 to the LNA 211. In FIG. 21, the transmitting/receiving switch 202 isomitted. The antenna 201 is connected to a bonding pad 103 through asignal line 217. The bonding pad 103 is connected to an input section ofthe LNA 211 through a signal line 218. Thus, a signal received by theantenna 201 is input to the LNA 211 through the bonding pad 103.

[0009]FIG. 22 shows a semiconductor circuit 100 including the bondingpad 103. The semiconductor circuit 100 includes a semiconductorsubstrate 101, an insulating layer 102 formed on the semiconductorsubstrate 101, and the bonding pad 103 formed on the insulating layer102. On the semiconductor substrate 101, a MOS transistor 113 is alsoformed. Herein, it is assumed that the MOS transistor 113 is included inthe input section of the LNA 211. A signal received by the antenna 201is input to the bonding pad 103 as a voltage signal V_(in). The bondingpad 103 is connected to a gate of the MOS transistor 113. Accordingly,the voltage signal V_(in) is applied to the gate of the MOS transistor113.

[0010]FIG. 23 shows an equivalent circuit of the semiconductor circuit100 shown in FIG. 22. In FIG. 23, C_(p) represents a parasiticcapacitance existing between the bonding pad 103 and the semiconductorsubstrate 101, and R_(p) represents a parasitic resistance existing on acurrent path from the bonding pad 103 to a ground potential.

[0011] The impedance Z of the bonding pad 103 is represented byexpression (1).

Z=(1/jωC _(p))+R _(p)  expression (1)

[0012] Herein, C_(p) represents a parasitic capacitance, and R_(p)represents a parasitic resistance. Letter j is a symbol indicating animaginary number. ω=2πf, and f represents a frequency of the signalinput to the bonding pad 103.

[0013] A power loss is generated by the impedance Z of the bonding pad103.

[0014] The power loss P_(a) based on the impedance Z of the bonding pad103 is represented by expression (2).

P _(a)=ω² C _(p) ² R _(p) |V _(in)|²/(1+ω² C _(p) ² R _(p)²)  expression (2)

[0015] Herein, V_(in) represents a voltage applied to the bonding pad103.

[0016]FIG. 24 shows the relationship among the parasitic resistanceR_(p), the parasitic capacitance C_(p) and the power loss P_(a). In FIG.24, it is assumed that the frequency f of the signal input to thebonding pad 103 is 1 GHz.

[0017] In the conventional communication system 200, when the RF section210 including the bonding pad 103 is formed on the GaAs substrate, thepower loss P_(a) is hardly a problem because the parasitic resistanceR_(p) is sufficiently large due to a very large resistance of the GaAssubstrate.

[0018] However, the GaAs substrate is very expensive. Furthermore, whenthe RF section 210 is formed on the GaAs substrate, the RF section 210and the baseband signal processing section 220 need to be formed ondifferent chips from each other since it is preferable that the basebandsignal processing section 220 is formed on a silicon substrate suitablefor fabrication of a CMOS structure. This causes a problem that it isdifficult to reduce the cost by forming main parts of the communicationsystem 200 on a single chip.

[0019] When the RF section 210 and the baseband signal processingsection 220 are formed on a single silicon chip, the parasiticcapacitance C_(p) is about 1 pF and the parasitic resistance R_(p) isabout 100 Ω. Therefore, the power lose based on the parasitic element ofthe bonding pad 103 is about several times as large as the power lossgenerated in the MOS transistor 113 (see FIG. 24). Accordingly, when theRF section 210 is formed on a silicon chip, the parasitic resistanceR_(p) needs to be reduced.

[0020] It is understood from FIG. 24 that the power loss P_(a) can bereduced also by reducing the parasitic capacitance C_(p). In order toreduce the parasitic capacitance C_(p), the size of the bonding pad 103needs to be reduced or the thickness of the insulating layer 102 needsto be increased. In consideration of the precision of the wire bonding,the size of the bonding pad 103 can only be reduced to a limited extent.It is difficult to increase the thickness of the insulating layer 102 inconsideration of the other circuit elements formed on the semiconductorsubstrate 101. As can be appreciated, it is not very practical to reducethe power loss P_(a) by reducing the parasitic capacitance C_(p).Accordingly, it is desirable to reduce the parasitic resistance R_(p)without substantially increasing the parasitic capacitance C_(p).

[0021]FIG. 25 shows the relationship between the frequency f of thesignal input to the bonding pad 103 and the power loss P_(a). It isunderstood from FIG. 25 that, as the frequency of the signal input tothe bonding pad 103 is increased, the parasitic resistance R_(p) needsto be reduced by a greater degree.

[0022] The parasitic resistance R_(p) also significantly influences thenoise characteristic of the MOS transistor 113 connected to the bondingpad 103. The minimum noise F_(min) of the MOS transistor 113 isgenerally represented by expression (3), which is referred to as the“fukui” equation.

F _(min)=1+2πfKC _(gs){square root}((R _(g) +R _(s) /gm)  expression (3)

[0023] Herein, C_(gs), represents a gate-source capacitance of the MOStransistor 113. K represents a transistor-inherent constant. R_(g)represents a gate resistance, and R_(s) represents a source resistance.

[0024] An increase in the parasitic resistance R_(p) is equivalent to anincrease in (R_(g)+R_(s)). As a result of the increase in the parasiticresistance R_(p). the minimum noise F_(min) of the MOS transistor 113 isincreased. In order to suppress the increase in the noise, the parasiticresistance R_(p) needs to be reduced.

[0025] A wireless receiver including an RF section and a baseband signalprocessing section formed on a single silicon substrate is disclosed in,for example, the following document.

[0026] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY 1996,pp. 880-889

[0027] FIG. 10 of the above-mentioned document shows a pad structureused in the RF section. The pad structure includes a first metal plate(Metal 1) and a second metal plate (Metal 2) facing each other. Thefirst metal plate is formed on a silicon substrate in the state of beinginsulated from the silicon substrate. The second metal plate is formedon the first metal plate in the state of being insulated from the firstmetal plate. The first metal plate is connected to a ground potential.

[0028] With such a pad structure, when an input voltage is applied tothe second metal plate, a current flowing from the second metal plate tothe first metal plate flows from the first metal plate to the groundpotential. Therefore, substantially no current flows in the siliconsubstrate. The parasitic resistance R_(p) in this case is represented bya sum of the resistance of the first metal plate and the interconnectresistance from the first metal plate to the ground. Accordingly, theparasitic resistance R_(p) is very small.

[0029] However, with the above-described pad structure, the first metalplate and the second metal plate face each other, and accordingly, theparasitic capacitance C_(p) is increased. The increase in the parasiticcapacitance C_(p) causes the cutoff frequency f_(t) of the MOStransistor connected to the second metal plate to be reduced.Furthermore, the increase in the parasitic capacitance C_(p) breaks theinsulating layer by a large force applied to the second metal plate atthe time of bonding. As a result, the second metal plate and the firstmetal plate may be undesirably shortcircuited, or the first metal plateand the silicon substrate may be undesirably shortcircuited.

[0030] The present invention for solving the above-described problemshas an objective of providing a semiconductor integrated circuit andsystem for reducing a power lose and noise caused by a parasitic elementof a bonding pad by reducing a parasitic resistance R_(p) withoutsubstantially increasing a parasitic capacitance C_(p). Anotherobjective of the present invention is to provide a semiconductorintegrated circuit and system having a bonding pad suitable forinputting and outputting a signal having a high frequency.

DISCLOSURE OF THE INVENTION

[0031] A semiconductor integrated circuit according to the presentinvention includes a bonding pad; a semiconductor substrate electricallyinsulated from the bonding pad, the semiconductor substrate having afirst region facing the bonding pad and a second region substantiallysurrounding at least a part of the first region; and setting means forsetting the second region substantially at an equipotential.

[0032] The setting means includes voltage supply means for supplying aprescribed voltage; and connecting means for electrically connecting thevoltage supply means to the second region of the semiconductorsubstrate.

[0033] In one embodiment, the connecting means includes a conductivesection electrically connected to the voltage supply means and aplurality of contact portions discretely formed, and the plurality ofcontact portions each electrically connect the conductive section to thesecond region of the semiconductor substrate.

[0034] In one embodiment, a shape of the second region of thesemiconductor substrate is determined by a shape of the conductivesection.

[0035] In one embodiment, the conductive section has a shapesubstantially surrounding the first region of the semiconductorsubstrate.

[0036] In one embodiment, the conductive section has a plurality ofbasic cells arranged in an array.

[0037] In one embodiment, the connecting means includes a conductivesection electrically connected to the voltage supply means and a contactportion continuously formed, and the contact portion electricallyconnects the conductive section to the second region of thesemiconductor substrate.

[0038] In one embodiment, the second region of the semiconductorsubstrate is located outside the first region of the semiconductorsubstrate.

[0039] In one embodiment, the second region of the semiconductorsubstrate is located inside the first region of the semiconductorsubstrate.

[0040] In one embodiment, the semiconductor integrated circuit furtherincludes a low resistance layer formed in at least a part of the firstregion of the semiconductor substrate.

[0041] In one embodiment, the equipotential is a ground potential.

[0042] A system according to the present invention includes atransmitting and receiving section for transmitting or receiving asignal; and a processing section for processing the signal to betransmitted or the signal received. The transmitting and receivingsection includes a pad structure including a bonding pad, asemiconductor substrate electrically insulated from the bonding pad, thesemiconductor substrate having a first region facing the bonding pad anda second region substantially surrounding at least a part of the firstregion, and means for setting the second region of the semiconductorsubstrate substantially at an equipotential.

[0043] In one embodiment, the transmitting and receiving sectiontransmits or receives the signal through an antenna.

[0044] In one embodiment, the transmitting and receiving sectiontransmits or receives the signal through an interface for connectingdifferent semiconductor chips.

[0045] In one embodiment, the signal has a frequency of 100 MHz or more.

[0046] In one embodiment, the transmitting and receiving section and theprocessing section are formed on a single semiconductor chip.

[0047] In one embodiment, the transmitting and receiving sectiontransmits and receives the signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0048]FIG. 1 is a view schematically showing a structure of asemiconductor integrated circuit 10 according to the present invention.

[0049]FIGS. 2A through 2C are views illustrating an equivalent circuitof the semiconductor integrated circuit 10 when a bonding pad 3 issquare.

[0050]FIGS. 3A through 3C are views illustrating an equivalent circuitof the semiconductor integrated circuit 10 when the bonding pad 3 ishexagonal.

[0051]FIGS. 4A through 4D are views illustrating an equivalent circuitof the semiconductor integrated circuit 10 when the bonding pad 3 iscircular.

[0052]FIG. 5 is a graph showing the relationship between the value of kand the value of a substrate resistance R_(sub).

[0053]FIGS. 6A through 6C are views illustrating an equivalent circuitof the semiconductor integrated circuit 10 when a region 5 is inside aregion 4.

[0054]FIGS. 7A through 7C are views illustrating an equivalent circuitof the semiconductor integrated circuit 10 when the region 5 is outsidethe region 4.

[0055]FIG. 8 is a graph showing the relationship between the innerradius r₂ of the region 5 and the power loss.

[0056]FIGS. 9A through 9E are views illustrating an equivalent circuitof the semiconductor integrated circuit 10 when there is a part of theregion 4 which is not surrounded by the region 5.

[0057]FIG. 10 is a graph showing the relationship between the centralangle θ₁ of a fan-shaped area 11 and the power loss.

[0058]FIGS. 11A through 11E are views showing a structure of asemiconductor integrated circuit 20 in a first example according to thepresent invention.

[0059]FIG. 12 is a view showing a shape of a conductive layer 14 a.

[0060]FIGS. 13A through 13C are views showing a structure of asemiconductor integrated circuit 30 in a second example according to thepresent invention.

[0061]FIGS. 14A through 14C are views showing a conductive layer 14having a plurality of basic cells arranged in an array.

[0062]FIGS. 15A through 15D are views showing a structure of asemiconductor integrated circuit 40 in a third example according to thepresent invention.

[0063]FIGS. 16A through 16C are views showing a structure of asemiconductor integrated circuit 50 in a fourth example according to thepresent invention.

[0064]FIGS. 17A through 17E are views showing a structure of asemiconductor integrated circuit 60 in a fifth example according to thepresent invention.

[0065]FIG. 18 is a view showing a structure of a communication system300 in a sixth example according to the present invention.

[0066]FIG. 19 is a plan view showing a shape of a 5×5 mesh typeconductive layer 14.

[0067]FIG. 20 is a view showing a structure of a conventionalcommunication system 200.

[0068]FIG. 21 is a view schematically showing an equivalent circuit froman antenna 201 to an LNA 211 of the conventional communication system200.

[0069]FIG. 22 is a view showing a structure of a semiconductorintegrated circuit 100 including a bonding pad 103.

[0070]FIG. 23 is a view showing an equivalent circuit of thesemiconductor integrated circuit 100.

[0071]FIG. 24 is a graph showing the relationship among the parasiticresistance R_(p), the parasitic capacitance C_(p) and the power lossP_(a).

[0072]FIG. 25 is a graph showing the relationship between the frequencyf of a signal input to the bonding pad 103 and the power loss P_(a).

BEST MODE FOR CARRYING OUT THE INVENTION

[0073] First, the basic principle of the present invention will bedescribed.

[0074]FIG. 1 schematically shows a structure of a semiconductorintegrated circuit 10 according to the present invention. Thesemiconductor integrated circuit 10 includes a semiconductor substrate 1and a bonding pad 3. The semiconductor substrate 1 and the bonding pad 3are electrically insulated from each other. Typically, the semiconductorsubstrate 1 and the bonding pad 3 are electrically insulated from eachother by providing an insulating layer between the semiconductorsubstrate 1 and the bonding pad 3. The semiconductor substrate 1 and thebonding pad 3 can be electrically insulated from each other by any othermethod.

[0075] The semiconductor substrate 1 has a region 4 facing the bondingpad 3 and a region 8 surrounding the region 4. The regions 4 and 5 aredefined in one of the surfaces of the semiconductor substrate 1, the onesurface facing the bonding pad 3.

[0076] The region 5 of the semiconductor substrate 1 is connected to avoltage supply section 6 for supplying a prescribed voltage potential.The prescribed voltage potential is preferably of a level at which thesemiconductor integrated circuit is stable in a system in which thecircuit is used. The prescribed voltage potential is, for example, aground potential. Alternatively, the prescribed voltage potential can bea power supply potential V_(DD). In this specification, such aprescribed voltage potential will be referred to as a “prescribedvoltage potential V_(ss)”. The voltage supply section 6 can be, forexample, a terminal which is set to a prescribed voltage potentialV_(ss). The region 5 of the semiconductor substrate 1 is setsubstantially at an equipotential by connecting the region 5 to thevoltage supply section 6 for supplying the prescribed voltage potentialV_(ss). The bonding pad 3 is supplied with a voltage V_(in) of an inputsignal.

[0077] In the semiconductor integrated circuit 10, the parasiticcapacitance C_(p) and the parasitic resistance R_(p) are calculated asfollows. In the following calculations, the bonding pad 3 and the region4 of the semiconductor substrate 1 facing the bonding pad 3 are assumedto be square. The shapes of the bonding pad 3 and the region 4 are notlimited to a square. As described below, the bonding pad 3 and theregion 4 can be polygons other than a square, or a circle.

[0078] The parasitic capacitance C_(p) is calculated in accordance withexpression (4). The parasitic capacitance C_(p) is defined as acapacitance existing between the bonding pad 3 and the semiconductorsubstrate 1.

C _(p) =a ² ×ε/d  expression (4)

[0079] Herein, a represents the length of one side of the bonding pad 3.ε is represented by a logical product of ε₁ and ε₀. ε₁ represents arelative dielectric constant of the insulating material for insulatingthe bonding pad 3 and the semiconductor substrate 1 from each other. ε₀represents a vacuum dielectric constant. d represents a distance betweenthe bonding pad 3 and the region 4.

[0080] The parasitic resistance R_(p) is calculated in accordance withexpression (5). The parasitic resistance R_(p) is defined as aresistance existing between the bonding pad 3 and the voltage supplysection 6.

R _(p)=ρ/16  expression (5)

[0081] Herein, ρ represents a sheet resistance of the semiconductorsubstrate 1.

[0082] Hereinafter, the reason why the parasitic resistance R_(p) isrepresented by expression (5) will be described.

[0083] It is assumed that as shown in FIG. 2A, the region 4 of thesemiconductor substrate 1 has four sub regions 4 a through 4 d. In thiscase, the resistance of each of the regions 4 a through 4 d isrepresented by a constant resistance R. As shown in FIG. 2B, theresistance R can be approximated to ρ/4. This is shown in expression(6).

R=ρ/4  expression (6)

[0084]FIG. 2C shows an equivalent circuit of the semiconductorintegrated circuit 10. The parasitic resistance R_(p) is equivalent tofour resistances R connected in parallel. This is shown in expression(7).

R _(p) =R/4  expression (7)

[0085] Expression (5) is obtained from expressions (6) and (7).

[0086] Hereinafter, the power loss of the semiconductor integratedcircuit 10 will be evaluated. The evaluation conditions are: f=1 GHz,ρ=400 Ω, and C_(p)=1 pF. f represents a frequency of a signal input tothe bonding pad 3. Since parasitic capacitance C_(p) is represented byexpression (4), the parasitic capacitance C_(p) can be easily made inthe order of about 1 pF. By substituting ρ=400 Ω (one of the evaluationconditions) into expression (5), the parasitic resistance R_(p) is 25 Ω.Thus, in the semiconductor integrated circuit 10 according to thepresent invention, the parasitic resistance R_(p) can be significantlylower than 100 Ω, at which the power loss is substantially the peakunder the same evaluation conditions. As a result, the power loss of thesemiconductor integrated circuit 10 can be reduced to about ¼ (see FIG.24) of the power loss when the parasitic resistance R_(p) is 100 Ω.

[0087] Under the evaluation conditions of f=1 GHz, ρ=1000 Ω, and C_(p)=1pF, the parasitic resistance R_(p) is 63 Ω. As a result, the power losscan be reduced to about ⅘ (see FIG. 24).

[0088] Since the parasitic resistance R_(p) is reduced, the noisegeneration can be suppressed.

[0089] The shapes of the bonding pad 3 and the region 4 are not limitedto a square. Even when the bonding pad 3 and the region 4 are hexagonal,the power loss of the semiconductor integrated circuit 10 can be reducedby surrounding the region 4 by the region 5.

[0090] It is assumed that, as shown in FIG. 3A, the region 4 of thesemiconductor substrate 1 has six sub regions 4 a through 4 f. In thiscase, the resistance of each of the regions 4 a through 4 f isrepresented by a constant resistance R. As shown in FIG. 3B, theresistance R can be approximated to ({square root}3/8)ρ. This is shownin expression (8).

R=({square root}3/8)ρ  expression (8)

[0091]FIG. 3C shows an equivalent circuit of the semiconductorintegrated circuit 10. The parasitic resistance R_(p) is equivalent tosix resistances R connected in parallel. This is shown in expression(9).

R _(p) =R/6  expression (9)

[0092] Expression (10) is obtained from expressions (8) and (9).

R _(p)=({square root}3/48)ρ  expression (10)

[0093] The power loss of the semiconductor integrated circuit 10 will beevaluated. The evaluation conditions are: f=1 GHz, ρ=400 Ω, and C_(p)=1pF. By substituting ρ=400 Ω (one of the evaluation conditions) intoexpression (10), the parasitic resistance R_(p) is about 14 Ω. Thus, inthe semiconductor integrated circuit 10 according to the presentinvention, the parasitic resistance R_(p) can be significantly lowerthan 100 Ω, at which the power loss is substantially the peak under thesame evaluation conditions. As a result, the power loss of thesemiconductor integrated circuit 10 can be reduced to about ⅕ (see FIG.24) of the power loss when the parasitic resistance R_(p) is 100 Ω.

[0094] Under the evaluation conditions of f=1 GHz, ρ=1000 Ω, and C_(p)=1pF, the parasitic resistance R_(p) is about 37 Ω. As a result, the powerloss can be reduced to about ½ (see FIG. 24).

[0095] Even when the bonding pad 3 and the region 4 are circular, thepower loss of the semiconductor integrated circuit 10 can be reduced bysurrounding the region 4 by the region 5.

[0096]FIG. 4A schematically shows a structure of the semiconductorintegrated circuit 10 in which the bonding pad 3 and the region 4 of thesemiconductor substrate 1 are circular. The region 5 is ring-shaped soas to surround the region 4. In the example shown in FIG. 4A, it isassumed that r₁=r₂. r₁ represents the radius of the bonding pad 3 andthe region 4 facing the bonding pad 3. r₂ represents the inner radius ofthe region 5.

[0097] Herein, the parasitic capacitance C_(p) and the parasiticresistance R_(p) are calculated using an “area division model”. It isassumed that the bonding pad 3 has a plurality of areas D₁ through D_(k)divided concentrically. The region 4 has a plurality of areas D′₁through D′_(k) corresponding thereto, respectively.

[0098]FIG. 4D shows an equivalent circuit of the semiconductorintegrated circuit 10 shown in FIG. 4A. In FIG. 4B, C(k−n) represents acapacitance existing between area D_((k−n)) of the bonding pad 3 andarea D′_((k−n)) of the semiconductor substrate 1. R represents aresistance existing between an outer periphery and an inner periphery ofarea D′_((k−n)) of the semiconductor substrate 1. Here, n is an integerof 0 or more and k−1 or less. R_(w) represents a resistance existingbetween the region 5 and the voltage supply section 6 for supplying 4prescribed voltage potential V_(ss).

[0099]FIG. 4C shows a simplified equivalent circuit of the semiconductorintegrated circuit 10. The semiconductor integrated circuit 10 isequivalent to a circuit including the parasitic capacitance C_(p) andthe parasitic resistance R_(p) connected in series. The parasiticcapacitance C_(p) is obtained by synthesizing k pieces of capacitancesC(1) through C(k). The parasitic resistance R_(p) is equivalent to acircuit including a substrate resistance R_(sub) and a resistance R_(w)connected in series. The parasitic resistance R_(p) can be considered tobe substantially equal to the substrate resistance R_(sub) with nosubstantial inconvenience because the resistance R_(w) is sufficientlysmall compared to the substrate resistance R_(sub). For example, theresistance R_(w) is 1 Ω. The substrate resistance R_(sub) can beobtained by synthesizing k pieces of resistances R.

[0100] The resistance R is calculated in accordance with expression(11).

R=ρ×θ/2π  expression (11)

[0101] Herein, ρ represents a sheet substrate of the semiconductorsubstrate 1. θ represents a central angle of a fan-shaped area 8. Theregion 4 can be approximated by arranging 2π/θ pieces of fan-shapedareas 8 having the central angle of θ around the center of the region 4.

[0102]FIG. 4D shows a structure of the fan-shaped area 8. The fan-shapedarea 8 includes k pieces blocks DD′₁ through DD′_(k). The position ofline segment A₁B₁ is determined so that the length of line segment B₀B₁is equal to the length of line segment A₀B₀. Quadrangle A₀A₁B₁B₀ isdefined as block DD′₁. In a similar manner, the position of line segmentA_(k−n)B_(k−n) is determined so that the length of line segmentB_(k−n−1)B_(k−n) is equal to the length of line segmentA_(k−n−1)B_(k−n−1). Quadrangle A_(k−n−1)A_(k−n)B_(k−n)B_(k−n−1) isdefined as block DD′_(k−n). Herein, n is an integer of 0 or more and k−1or less. When θ is sufficiently smaller than 1, block DD′_(k−n) can beregarded as a square since, when θ<<1, it can be regarded that thelength of line segment A_(k−n)B_(k−n) is nearly equal to the length ofline segment A_(k−n−1)B_(k−n−1).

[0103] In the following description, it is assumed that θ=1/100. In thiscase, block DD′_(k−n) can be regarded as a square. Accordingly, theresistance between line segment A_(k−n)B_(k−n) and line segmentA_(k−n−1)B_(k−n−1) is equal to the sheet resistance ρ of thesemiconductor substrate 1. Area D′_(k−n) can be approximated byarranging 2π/θ pieces of blocks DD′_(k−n) around the center of theregion 4. Accordingly, the resistance existing between an outerperiphery and an inner periphery of area D′_(k−n) is represented byexpression (11).

[0104] The capacitance C(k−n) is calculated in accordance withexpression (12).

C(k−n)=cap×π×r ₁ ²(1−θ)^(2k−2n−2)θ(2−θ)×2π/θ  expression (12)

[0105] Herein, cap represents a capacitance per unit area. Here, it isassumed that cap×π×r₁ ²=1 pF in order to simplify the calculation.

[0106]FIG. 5 shows the results of simulation based on the equivalentcircuit shown in FIG. 4B. The conditions for simulation are f=1 GHz andρ=1000 Ω. In FIG. 5, the horizontal axis indicates the value of k, andthe vertical axis indicates the value of the substrate resistanceR_(sub) which is obtained by synthesizing k pieces of resistances R. Itis appreciated that, in the range of k≧200, the value of the substrateresistance R_(sub) is converged to 40 Ω. As the value of k is higher,the precision of the value of the substrate resistance R_(sub) becomeshigher. However, when the value of k is excessively high, thecalculation time required for the simulation is extended. In actuality,k=460 is sufficient. As can be appreciated, according to the simulationperformed based on the area division model, the parasitic resistanceR_(p) is reduced to about {fraction (1/25)} of the sheet resistance ρ ofthe semiconductor substrate 1. As a result, the power loss of thesemiconductor integrated circuit 10 can be reduced to about ½ of thepower loss when the parasitic resistance R_(p) is 100 Ω.

[0107] The regions 4 and 5 of the semiconductor substrate 1 can havevarious modifications in terms of shapes and arrangements. Suchmodifications should be construed to be included in the scope of thepresent invention as long as the above-described principle of thepresent invention is applied. At least the modifications described beloware included in the scope of the present invention.

[0108] In the semiconductor integrated circuit 10, the inner peripheryof the region 5 does not need to match the outer periphery of the region4. At least a part of the region 5 can be located inside the region 4 aslong as a similar effect is obtained with the case where the innerperiphery of the region 5 matches the outer periphery of the region 4.Alternatively, at least a part of the region 5 can be located outsidethe region 4.

[0109]FIG. 6A schematically shows a structure of the semiconductorintegrated circuit 10 in which the region 5 is located inside the region4. In the example shown in FIG. 6A, r₁>r₂. Herein, r₁ represents theradius of the bonding pad 3 and the region 4 facing the bonding pad 3.r₂ represents the inner radius of the region 5.

[0110]FIG. 6B shows an equivalent circuit of the semiconductorintegrated circuit 10 shown in FIG. 6A. It is assumed thatr₂=r₁(1−θ)^(k−n)(n<k). In FIG. 6B, identical elements with those shownin FIG. 4B bear identical reference numerals.

[0111]FIG. 6C shows a simplified equivalent circuit of the semiconductorintegrated circuit 10. The semiconductor integrated circuit 10 isequivalent to a circuit including a parasitic capacitance C_(p) and aparasitic resistance R_(p) connected in series. The parasiticcapacitance C_(p) is obtained by synthesizing k pieces of capacitancesC(1) through C(k). The parasitic resistance R_(p) is equivalent to acircuit including a substrate resistance R_(sub) and a resistance R_(w)connected in series. The substrate resistance R_(sub) can be obtained bysynthesizing k pieces of resistances R.

[0112]FIG. 7A schematically shows a structure of the semiconductorintegrated circuit 10 in which the region 5 is located outside theregion 4. In the example shown in FIG. 7A, R₁<r₂. Herein, r₁ representsthe radius of the bonding pad 3 and the region 4 facing the bonding pad3. r₂ represents the inner radius of the region 5.

[0113]FIG. 7B shows an equivalent circuit of the semiconductorintegrated circuit 10 shown in FIG. 7A. It is assumed thatr₂=r₁(1−θ)^(k−n)(n>k). In FIG. 7B, identical elements with those shownin FIG. 4B bear identical reference numerals.

[0114]FIG. 7C shows a simplified equivalent circuit of the semiconductorintegrated circuit 10. The semiconductor integrated circuit 10 isequivalent to a circuit including a parasitic capacitance C_(p) and aparasitic resistance R_(p) connected in series. The parasiticcapacitance C_(p) is obtained by synthesizing k pieces of capacitancesC(1) through C(k). The parasitic resistance R_(p) is equivalent to acircuit including a substrate resistance R_(sub) and a resistance R_(w)connected in series. The substrate resistance R_(sub) can be obtained bysynthesizing k pieces of resistances R and (n−k)R. Herein, (n−k)Rrepresents a resistance existing between the outer periphery of theregion 4 and the inner periphery of the region 5.

[0115]FIG. 8 shows the results of simulation based on the equivalentcircuit shown in FIGS. 6B and 7B. The conditions for simulation arer₁=100 μm, f=1 GHz and ρ=1000 Ω. In FIG. 8, the horizontal axisindicates the value of the inner radius r₂ of the region 5, and thevertical axis indicates the power loss of the semiconductor integratedcircuit 10. It is understood from FIG. 8 that the power loss can bereduced at a point at which r₁=r₂ and the vicinity thereof. For example,in order to make the power loss of the semiconductor integrated circuit10 to a tolerable value P_(γ) (for example, 2.0 mW) or less, the innerradius r₂ of the region 5 is set so as to fulfill 45 μm≦r₂≦110 μm. Inthis manner, by surrounding at least a part of the region 4 by theregion 5, the power loss of the semiconductor integrated circuit 10 canbe reduced.

[0116] In the semiconductor integrated circuit 10, the region 5 does notneed to completely surround the region 4. There can be a part of theregion 4 which is not surrounded by the region 5 as long as a similareffect is obtained to the case where the region 5 completely surroundsthe region 4.

[0117]FIG. 9A schematically shows a structure of the semiconductorintegrated circuit 10 in which there is a part of the region 4 which isnot surrounded by the region 5. In the example shown in FIG. 9A, theregion 5 does not exist in a part corresponding to a fan-shaped area 11having a central angle θ₁, r₁=r₂. Herein, r₁ represents the radius ofthe bonding pad 3 and the region 4 facing the bonding pad 3. r₂represents the inner radius of the region 5.

[0118] Herein, the parasitic capacitance C_(p) and the parasiticresistance R_(p) are calculated using an “area division model”. It isassumed that the bonding pad 3 has a plurality of areas D₁ through D_(k)divided concentrically. The region 4 has a plurality of areas D′₁through D′_(k) corresponding thereto, respectively. Areas D′₁ throughD′_(k) do not exist in a part corresponding to the fan-shaped area 11having the central angle θ₁.

[0119]FIG. 9B shows the fan-shaped area 11 having the central angle θ₁.It is assumed that the fan-shaped area 11 has a plurality of areas F′₁through F′_(k) divided concentrically, and that each of the plurality ofareas F′₁ through F′_(k) has 2 m pieces of blocks. Among the 2 m piecesof blocks included in area F′_(k−n), m pieces of block corresponding tothe central angle θ₁/2 are defined as blocks FF′_(j,k−n). Herein, j isan integer of 1 or more and m or less. m=θ₁/2θ.

[0120]FIG. 9C three-dimensionally shows an equivalent circuit regardingthem pieces of blocks FF′_(1,k−n) through FF′_(mk−n) included in areaF′_(k−n). In FIG. 9C, Ca(j, k−n) represents a capacitance existingbetween area D_(k−n) of the bonding pad 3 and block FF′_(j, k−n) of thesemiconductor substrate 1. rsh represents a resistance of blockFF′_(j, k−n). The resistance rsh is equal to the sheet resistance ρ ofthe semiconductor substrate 1. Herein. j is an integer of 1 or more andm or less.

[0121]FIG. 9D shows an equivalent circuit of the semiconductorintegrated circuit 10 shown in FIG. 9A. In FIG. 9D, C1(k−n) represents acapacitance existing between area D_(k−n) of the bonding pad 3 and areaD′_(k−n) of the semiconductor substrate 1. R1 represents a resistanceexisting between an outer periphery and an inner periphery of areaD′_(k−n) of the semiconductor substrate 1. Herein, n is an integer of 0or more and k−1 or less. R_(w) represents a resistance existing betweenthe region 5 and the voltage supply section 6 for supplying theprescribed voltage potential V_(ss).

[0122]FIG. 9E shows a simplified equivalent circuit of the semiconductorintegrated circuit 10. The semiconductor integrated circuit 10 isequivalent to a circuit including a parasitic capacitance C_(p) and aparasitic resistance R_(p) connected in series. The parasiticcapacitance C_(p) is obtained by synthesizing k pieces of capacitancesC1(1) through C1(k)and mk pieces of capacitances Ca(1, 1) through Ca(m,k−1). The parasitic resistance R_(p) is equivalent to a circuitincluding a substrate resistance R_(sub) and a resistance R_(w)connected in series. The substrate resistance R_(sub) can be obtained bysynthesizing k pieces of resistances R1 and mk pieces of resistancesrsh.

[0123] The resistance R1 is calculated in accordance with expression(13).

R=ρ×θ/(2π−θ₁)  expression (13)

[0124] The capacitance C1(k−n) is calculated in accordance withexpression (14).

C 1(k−n)=cap×π×r ₁ ²(1−θ)^(2k−2n−2)θ(2−θ)×(2π−θ₁)/θ  expression (14)

[0125] The capacitance Ca(j, k−n) is calculated in accordance withexpression (15 ).

Ca(j, k−n)=2×cap×π×r ₁ ²(1−θ)^(2k−2n−2)θ(2−θ)  expression (15)

[0126] Herein, cap represents a capacitance per a unit area. Herein, itis assumed that cap×π×r₁ ²=1 pF in order to simplify the calculation.

[0127]FIG. 10 shows the results of simulation based on the equivalentcircuit shown in FIG. 9D. The conditions for simulation are r₁=r₂=100μm, f=1 GHz and ρ=1000 Ω. In FIG. 10, the horizontal axis indicates thevalue of the central angle θ₁, and the vertical axis indicates the powerloss of the semiconductor integrated circuit 10. It is understood fromFIG. 10 that the power loss can be reduced even when there is a part ofthe region 4 which is not surrounded by the region 5 as long as the partis sufficiently small. For example, in order to make the power loss ofthe semiconductor integrated circuit 10 to a tolerable value P_(γ) (forexample, 2.0 mW) or less, the central angle θ₁ is set so as to fulfillθ₁≦1.7 radian. Thus, by substantially surrounding the region 4 by theregion 5, the power loss of the semiconductor integrated circuit 10 canbe reduced.

[0128] In this specification, the expression “the region 5 substantiallysurrounds the region 4” is defined to include a structure where “theregion 5 completely surrounds the region 4” and a structure where “thereis a part of the region 4 which is not surrounded by the region 5 oncondition that the power loss is a tolerable value or less”.

[0129] It is not necessary that the entirety of the region 5 be set to aprescribed voltage potential. At least a part of the region 5 can be setto a different voltage potential from the prescribed voltage potentialas long as a similar effect is obtained to the case where the entiretyof the region 5 is set to the prescribed voltage potential. For example,when a plurality of contact portions are discretely arranged on theregion 5 and are connected to the voltage supply section 6 for supplyinga prescribed voltage potential V_(ss), the portions of the region 5which are in contact with the contact portions are set to the prescribedvoltage potential V_(ss), but the other portions are not precisely setto the prescribed voltage potential V_(ss). However, the entirety of theregion 5 can be regarded as substantially set to the prescribed voltagepotential V_(ss) where the plurality of contact portions are arranged onthe region 5 so that a distance between every two adjacent contactportions is sufficiently small. Accordingly, when a plurality of contactportions are used to set the region 5 to a prescribed voltage potentialV_(ss), the number of contact portions is preferably as large aspossible.

[0130] Hereinafter, specific examples according to the invention will bedescribed.

EXAMPLE 1

[0131]FIG. 11A is a plan view of a semiconductor integrated circuit 20in a first example according to the present invention. FIG. 11B is across-sectional view of the semiconductor integrated circuit 20 takenalong line A-A′ shown in FIG. 11A.

[0132] The semiconductor integrated circuit 20 includes a semiconductorsubstrate 1, an insulating layer 2 formed on the semiconductor substrate1, and a bonding pad 3 formed on the insulating layer 2. The bonding pad3 is connected to another circuit through an interconnect 12.Accordingly, a signal input to the bonding pad 3 is transmitted to theanother circuit through the interconnect 12. In FIG. 11B, a MOStransistor 13 is shown as an example of the circuit connected to thebonding pad 3.

[0133] The semiconductor integrated circuit 20 further includes aconductive layer 14 and a plurality of contact holes 15 discretelyformed. The conductive layer 14 is formed in the insulating layer 2. Theconductive layer 14 is connected to a bonding pad 17 through a contacthole 16. The bonding pad 17 is connected to a voltage supply section 6(FIG. 1) for supplying a prescribed voltage potential V_(ss). Thevoltage supply section 6 can be, for example, a terminal set to aprescribed voltage potential V_(ss). The plurality of contact holes 15each electrically connect the conductive layer 14 and the semiconductorsubstrate 1 to each other.

[0134]FIG. 11C is a plan view showing the shape of the conductive layer14. In the example shown in FIG. 11C, the conductive layer 14 isframe-shaped and located outside a region 4 on the semiconductorsubstrate 1 facing the bonding pad 3. In FIG. 11C, black squaresindicate positions of the contact holes 15. In FIG. 11C, line A-A′correspond to the line A-A′ shown in FIG. 11A.

[0135] Thus, the bonding pad 3 and the conductive layer 14 arepreferably located so as not to face each other. The reason for this isthat when the bonding pad 3 and the conductive layer 14 face each other,a parasitic capacitance C_(p) existing between the bonding pad 3 and theconductive layer 14 increases. The increase in the parasitic capacitanceC_(p) causes an increase in the power loss of the semiconductorintegrated circuit 20.

[0136] The bonding pad 3 and the conductive layer 14 are preferablylocated so as not to face each other also from the viewpoint ofreliability of the semiconductor integrated circuit 20. The reason forthis is that when the bonding pad 3 and the conductive layer 14 faceeach other, the bonding pad 3 and the conductive layer 14 may beundesirably shortcircuited by a large force applied to the bonding pad 3at the time of bonding. When the bonding pad 3 and the conductive layer14 are located so as not to face each other, there is no undesirablepossibility of shortcircuiting between the bonding pad 3 and theconductive layer 14.

[0137]FIG. 11D is a plan view showing the shape of a region 5 of thesemiconductor substrate 1 immediately below the conductive layer 14. Asshown in FIG. 11D, the shape of the region 5 is identical with the shapeof the conductive layer 14. As can be appreciated, the shape of theregion 5 is determined by the shape of the conductive layer 14.

[0138] The region 5 surrounds the region 4 facing the bonding pad 3. Thevoltage potential of the region 5 is set to the prescribed voltagepotential V_(ss) since the region 5 is connected to the voltage supplysection 6 for supplying the prescribed voltage potential V_(ss) throughthe contact holes 15, the conductive layer 14, the contact hole 16 andthe bonding pad 17. The number of the contact holes 15 is preferably aslarge as possible since where the number of the contact holes 15 issufficiently large, the entirety of the region 5 can be regarded as setto the prescribed voltage potential V_(ss), not only the portions of theregion 5 which are in contact with the contact holes 15.

[0139]FIG. 11E shows an equivalent circuit of the semiconductorintegrated circuit 20. In FIG. 11E, C_(p) represents a parasiticcapacitance existing between the bonding pad 3 and the semiconductorsubstrate 1. R_(p) represents a parasitic resistance existing betweenthe bonding pad 3 and the voltage supply section 6. The parasiticresistance R_(p) is equivalent to a circuit including a substrateresistance R_(sub) and a resistance R_(w) connected in series. Herein,the resistance R_(w) is a resistance existing between the region 5 andthe voltage supply section 6 for supplying the prescribed voltagepotential V_(ss).

[0140] Thus, by setting the region 5 surrounding the region 4 facing thebonding pad 3 substantially at an equipotential, the parasiticresistance R_(p) can be reduced without substantially increasing theparasitic capacitance C_(p) based on the above-described principle ofthe present invention. As a result, the power loss of the semiconductorintegrated circuit 20 is reduced and the noise generation is suppressed.

[0141] The power loss caused by a parasitic element in the isinterconnect 12 can be reduced by forming the region 5 so as tosubstantially surround an area of the semiconductor substrate 1 facingthe interconnect 12 as well as the region 4 facing the bonding pad 3.The reason for this in that the basic principle described regarding thebonding pad 3 can be applied to the interconnect 12. Due to such astructure, the entire power loss of the semiconductor integrated circuit20 can further be reduced.

[0142]FIG. 12 is a plan view showing the shape of a conductive layer 14a formed in consideration of the interconnect 12. The conductive layer14 a does not completely surround the region 4. Nonetheless, asdescribed with reference to FIG. 10, when the part of the region 4 whichis not surrounded by the region 5 is sufficiently small, a similaraffect to the above-described effect is obtained. The width of theinterconnect 12 can be equal to the length of a side of the bonding pad3. In this case also, the conductive layer 14 a can be formed so as tomatch the shape of the interconnect 12 and the bonding pad 3.

[0143] Hereinafter, preferable properties of the semiconductor substrate1, the insulating layer 2, the bonding pad 3 and the conductive layer 14will be described.

[0144] The semiconductor substrate 1 can be, for example, a p-typesilicon substrate. However, the polarity of the semiconductor substrate1 is not essential to the present invention. The semiconductor substrate1 can be an n-type silicon substrate. A material of the insulating layer2 is preferably SiO₂ or the like. The thickness of the insulating layer2 is preferably about 1 μm to 2 μm. The bonding pad 3 is preferably asquare having a side of about 100 μm. As the material of the bonding pad3, a metal material having a low conductivity is usable. The material ofthe bonding pad 3 is preferably aluminum, gold or copper. The materialof the conductive layer 14 is preferably aluminum, gold or copper.

[0145] Hereinafter, a method for fabricating the semiconductorintegrated circuit 20 will be described. On the semiconductor substrate1, an insulating layer 2 a (FIG. 11B) is formed as a first insulatinglayer. In the insulating film 2 a, the contact holes 15 are formed so asto be electrically connected to the semiconductor substrate 1. Then, theconductive layer 14 as a first conductive layer is formed on theinsulating film 2 a. The conductive layer 14 is electrically connectedto the contact holes 15. On the conductive layer 14, an insulating layer2 b (FIG. 11B) is formed as a second insulating layer. In the insulatinglayer 2 b, contact holes 16 are formed so as to be electricallyconnected to the conductive layer 14, and contact holes 18 are formed soas to be electrically connected to the MOS transistor 13. Then, thebonding pad 3 and 17 and the interconnect 12 are formed as a secondconductive layer on the insulating layer 2 b. The bonding pad 17 iselectrically connected to the contact holes 16. The bonding pad 3 andthe interconnect 12 are electrically connected to each other.

[0146] A method for fabricating the MOS transistor 13 will not bedescribed in detail. The MOS transistor 13 is fabricated by a well-knownmethod. In the above, the method for fabricating the semiconductorintegrated circuit 20 has been described mainly regarding a method forfabricating the pad structure in the semiconductor integrated circuit20.

[0147] As can be appreciated, the semiconductor integrated circuit 20does not require any additional fabrication step to a usual method forfabricating the MOS transistor. Accordingly, no new process is needed tobe developed to fabricate the semiconductor integrated circuit 20. Thisis effective to reduce the fabrication cost of the semiconductorintegrated circuit 20. Such a fabrication method does not significantlyincrease the layout area for the semiconductor integrated circuit 20.

EXAMPLE 2

[0148]FIG. 13A is a cross-sectional view of a semiconductor integratedcircuit 30 in a second example according to the present invention. InFIG. 13A, identical elements with those shown in FIGS. 11A through 11Ebear identical reference numerals, and detailed descriptions thereofwill be omitted.

[0149]FIG. 13B is a plan view showing the shape of the conductive layer14. In the example shown in FIG. 13B, the conductive layer 14 isframe-shaped and located outside the region 4 on the semiconductorsubstrate 1 facing the bonding pad 3. In FIG. 13B, black squaresindicate positions of the contact holes 15.

[0150]FIG. 13C is a plan view showing the shape of a low resistancelayer 19 formed in the semiconductor substrate 1.

[0151] By forming the low resistance layer 19 in the semiconductorsubstrate 1 as shown in FIGS. 13A and 13C, the parasitic resistanceR_(p) can further be reduced. The reason for this is that formation ofthe low resistance layer 19 in the semiconductor substrate 1 provides asimilar effect to reduction of the sheet resistance of the semiconductorsubstrate 1. Herein, the low resistance layer 19 is defined as a layerhaving a sheet resistance which is smaller than the sheet resistance ofthe semiconductor substrate 1 by one or more orders of magnitude.

[0152] The low resistance layer 19 can be formed of, for example, amaterial doped with impurities having the same polarity as that of thesemiconductor substrate 1. Alternatively, the low resistance layer 19can be formed of a material doped with impurities having the oppositepolarity to that of the semiconductor substrate 1. Still alternatively,the low resistance layer 19 can be formed of an epitaxial layer.

[0153] The low resistance layer 19 does not need to be formed at theentire face of the semiconductor substrate 1. The effect of reducing theparasitic resistance R_(p) is obtained by forming the low resistancelayer 19 in at least a part of the region 4 of the semiconductorsubstrate 1 facing the bonding pad 3. The reason for this is thatreduction in the sheet resistance of a part of the semiconductorsubstrate 1 immediately below the bonding pad 3 contributes to thereduction in the parasitic resistance R_(p). In order to enhance theeffect of reducing the parasitic resistance R_(p), the low resistancelayer 19 is preferably formed so as to cover the region 4 of thesemiconductor substrate 1.

EXAMPLE 3

[0154] In the above-described first and second examples, the conductivelayer 14 is frame-shaped. The conductive layer 14 is not limited to sucha shape. For example, the conductive layer 14 can have a plurality ofbasic cells arranged in an array. The basic cells can be of an arbitrarypolygon or circle. For example, the basic cells can be square,rectangular or hexagonal.

[0155]FIGS. 14A, 14B and 14C show examples of the conductive layer 14having a plurality of basic cells arranged in an array. In FIG. 14A,rectangular basic cells are arranged in lattice. In FIG. 14B, squarebasic cells are arranged in mesh. In FIG. 14C, hexagonal basic cells arearranged in a honeycomb manner.

[0156] The value of the parasitic resistance R_(p) can be controlled inaccordance with the number of basic cells arranged on the region 4 ofthe semiconductor substrate 1 facing the bonding pad 3. For example, theparasitic resistance R_(p) can be reduced to about 1 Ω by arranging 16hexagonal basic cells in a honeycomb manner as shown in FIG. 14C on theregion 4 of the semiconductor substrate 1. As a result, the power lossis reduced to about {fraction (1/70)}. the deterioration by noise can bereduced to a substantially negligible level.

[0157] When 100 hexagonal the basic cells are arranged in a honeycombmanner as shown in FIG. 14C, the parasitic resistance R_(p) can bereduced to about 1 Ω when evaluated under the conditions of f=1 GHz andρ=1000 Ω. As a result, the power loss is reduced to about {fraction(1/50)}. The deterioration by noise can be reduced to a substantiallynegligible level.

[0158]FIG. 15A is a plan view of a semiconductor integrated circuit 40including the conductive layer 14 formed of a mesh layer. FIG. 15B is across-sectional view of the semiconductor integrated circuit 40 takenalong line A-A′ shown in FIG. 15A. In FIGS. 15A and 15B, identicalelements with those shown in FIGS. 11A through 11E bear identicalreference numerals and detailed descriptions thereof will be omitted.

[0159]FIG. 15C is a plan view showing the shape of the conductive layer14. In FIG. 15C, black squares indicate positions of the contact holes15. In FIG. 15C, line A-A′ correspond to the line A-A′ shown in FIG.15A.

[0160]FIG. 15D is a plan view showing the shape of a region 5 of thesemiconductor substrate 1 immediately below the conductive layer 14. Asshown in FIG. 15D, the region 5 surrounds a part of the region 4 facingthe bonding pad 3. The voltage potential of the region 5 is set to aprescribed voltage potential V_(ss).

[0161] Thus, by setting the region 5 surrounding at least a part of theregion 4 facing the bonding pad 3 substantially at an equipotential, theparasitic resistance R_(p) can be reduced without substantiallyincreasing the parasitic capacitance C_(p) based on the above-describedprinciple of the present invention. As a result, the power loss of thesemiconductor integrated circuit 40 is reduced and the noise generationis suppressed.

[0162] The parasitic resistance R_(p) can further be reduced bycombining the conductive layer having a plurality of basic cellsarranged in an array and the low resistance layer described in thesecond example 2.

EXAMPLE 4

[0163] In the above-described first through third examples, the shapeand the position of the region 5 are defined using the conductive layer14 and the contact holes 15. It is not indispensable to use theconductive layer 14. A prescribed voltage potential V_(ss) can besupplied to the region 5 without using the conductive layer 14.

[0164] The contact holes 15 do not need to be discretely formed. It israther preferable that the contact holes 15 are formed continuously inorder to uniformly set the region 5 to a prescribed voltage potentialV_(ss).

[0165]FIG. 16A is a plan view of a semiconductor integrated circuit 50in which the region 5 of the semiconductor substrate 1 is set to aprescribed voltage potential V_(ss) using a contact portion 15 acontinuously formed, without using the conductive layer 14. FIG. 16B isa cross-sectional view of the semiconductor integrated circuit 50 takenalong line A-A′ shown in FIG. 16A. In FIGS. 16A and 16B, identicalelements with those shown in FIGS. 11A through 11E bear identicalreference numerals and detailed descriptions thereof will be omitted.

[0166] The contact portion 15 a is continuously formed so as to surroundthe region 4 of the semiconductor substrate 1 facing the bonding pad 3.A part of the contact portion 15 a is connected to the bonding pad 17which is set to the prescribed voltage potential V_(ss).

[0167]FIG. 16C is a plan view showing the shape of the region 5 of thesemiconductor substrate 1 which is set to the prescribed voltagepotential V_(ss). The shape of the region 5 is defined by a part wherethe contact portion 15 a contacts the semiconductor substrate 1. Thus,the region 5 set to the prescribed voltage potential V_(ss) can bedefined around the region 4 using only the contact portion 15 a withoutusing the conductive layer 14. The part where the contact portion 15 acontacts the semiconductor substrate 1 can be formed continuously byusing the continuously formed contact portion 15 a. Thus, the voltagepotential of the region 5 can be set to the prescribed voltage potentialV_(ss) more uniformly than the case where the region 5 is set to theprescribed voltage potential V_(ss) using the plurality of contact holes15 discretely formed.

[0168] Thus, by setting the region 5 surrounding at least a part of theregion 4 facing the bonding pad 3 substantially at an equipotential, theparasitic resistance R_(p) can be reduced without substantiallyincreasing the parasitic capacitance C_(p) based on the above-describedprinciple of the present invention. As a result, the power loss of thesemiconductor integrated circuit 50 is reduced and the noise generationis suppressed.

[0169] The parasitic resistance R_(p) can further be reduced bycombining the contact portion 15 a continuously formed and the lowresistance layer described in the second example 2.

EXAMPLE 5

[0170]FIG. 17A is a plan view of a semiconductor integrated circuit 60in a fifth example according to the present invention. FIG. 17B is across-sectional view of the semiconductor integrated circuit 60 takenalong line A-A′ shown in FIG. 17A. In FIGS. 17A and 17B, identicalelements with those shown in FIGS. 11A through 11E bear identicalreference numerals and detailed descriptions thereof will be omitted.

[0171] A metal layer 61 is formed on a part of a surface of thesemiconductor substrate 1 facing the bonding pad 3. The metal layer 61is connected to the bonding pad 17 set to a prescribed voltage potentialV_(ss) through contact holes 16. The metal layer 61 is formed so as tosubstantially surround the region 4 of the semiconductor substrate 1facing the bonding pad 3. Thus, the region 5 substantially surroundingthe region 4 of the semiconductor substrate 1 is set to the prescribedvoltage potential V_(ss).

[0172]FIG. 17C is a plan view showing the shape of the metal layer 61.In the example show in FIG. 17C, the metal layer 61 is frame-shaped andis located outside the region 4 of the semiconductor substrate 1 facingthe bonding pad 3. In FIG. 17C, black squares indicate positions of thecontact holes 16. In FIG. 17C, line A-A′ correspond to the line A-A′shown in FIG. 17A.

[0173]FIG. 17D is a plan view showing the shape of the region 5 of thesemiconductor substrate 1 in contact with the metal layer 61. As shownin FIG. 17D, the shape of the region 5 is identical with the shape ofthe metal layer 61.

[0174] In lieu of the frame-shaped metal layer 61 shown in FIG. 17C, ametal layer 62 having the shape of a flat plate can be used.

[0175]FIG. 17E is a plan view showing the shape of the metal layer 62.In the example shown in FIG. 17E, the metal layer 62 is arranged so asto cover the region 4 of the semiconductor substrate 1 facing thebonding pad 3. In FIG. 17E, black squares indicate positions of thecontact holes 16. In FIG. 17E, line A-A′ correspond to the line A-A′shown in FIG. 17A.

[0176] When the metal layer 62 is formed on the semiconductor substrate1, the region 4 is set to the prescribed voltage potential V_(ss) inaddition to the region 5 substantially surrounding the region 4 since apart of the semiconductor substrate 1 in contact with the metal layer 62includes the region 4. A structure in which the voltage potential of theregion 4 is set to the prescribed voltage potential V_(ss) is includedin the scope of the present invention as long as the voltage potentialof the region 5 is set to the prescribed voltage potential V_(ss). Thus,a structure in which the voltage potential of the region 4 is set to theprescribed voltage potential V_(ss) and a structure in which the voltagepotential of the region 4 is not set to the prescribed voltage potentialV_(ss) are both included in the scope of the present invention as longas the voltage potential of the region 5 is set to the prescribedvoltage potential V_(ss).

[0177] Preferable materials for the metal layers 61 and 62 includealuminum, gold and copper.

[0178] Thus, by setting the region 5 surrounding at least a part of theregion 4 facing the bonding pad 3 substantially at an equipotential, theparasitic resistance R_(p) can be reduced without substantiallyincreasing the parasitic capacitance C_(p) based on the above-describedprinciple of the present invention. As a result, the power loss of thesemiconductor integrated circuit 60 is reduced and the noise generationis suppressed.

[0179] The parasitic resistance R_(p) can further be reduced bycombining the metal layer 61 or 62 and the low resistance layerdescribed in the second example 2.

EXAMPLE 6

[0180]FIG. 18 shows a communication system 300 in a sixth exampleaccording to the present invention. The communication system 300includes an RF section 310 for transmitting or receiving a signal, and abaseband signal processing section 320 for processing a signal to betransmitted or a signal received. The RF section 310 and the basebandsignal processing section 320 are provided on a single semiconductorchip 303. The semiconductor chip 303 is preferably a silicon substratesince the silicon substrate is suitable for formation of a CMOS.

[0181] An antenna 301 receives a signal having a high frequency. Thesignal has a frequency of, for example, 100 MHz or more. The signalreceived by the antenna 301 is input to a low noise amplifier (LNA) 311of the RF section 310 through a transmitting/receiving switch 302. TheLNA 311 amplifies the received signal. The amplified signal is input toa mixer 313 through a filter 312. The mixer 313 mixes the signal outputfrom the filter 312 and an oscillation signal output from an oscillator314. The output from the mixer 313 is supplied to the baseband signalprocessing signal 320.

[0182] The baseband signal processing section 320 includes a converter321 and a digital signal processor (DSP) 322. The converter 321 convertsthe analog signal output from the mixer 313 into a digital signal. TheDSP 322 processes the digital signal.

[0183] The digital signal processed by the DSP 322 is converted into ananalog signal by the converter 321. A mixer 315 of the RF section 310mixes the signal output from the converter 321 and an oscillation signaloutput from the oscillator 314. A power amplifier (PA) 316 amplifies theoutput from the mixer 315. The amplified signal is transmitted from theantenna 301 through the transmitting/receiving switch 302.

[0184] The RF section 310 includes a pad structure 311 a used forinputting a signal to the LNA 311 and a pad structure 316 a used foroutputting a signal from the PA 316. The pad structure 311 a and the padstructure 316 a each can have any structure of the semiconductorintegrated circuits according to the present invention described withreference to FIGS. 1 through 17. The pad structure 311 a allows thepower loss and noise generation caused when a signal is input to the LNA311 to be reduced. The pad structure 316 a allows the power loss andnoise generation caused when a signal is output from the PA 316 to bereduced.

[0185] The communication system 300 can both transmit and receive asignal. Alternatively, the communication system 300 can be only fortransmitting a signal or only for receiving a signal.

[0186] As described above, the pad structure 311 a is used for inputtinga signal received by the antenna 301 to another signal circuit (e.g.,LNA 311). The pad structure 311 a is not limited to such a use. The padstructure 316 a is used for outputting a signal to be transmitted fromanother circuit (e.g., PA 316) through the antenna 301. The padstructure 316 a is not limited to such a use. For example, in anembodiment in which the pad structure 311 a is provided on a firstsemiconductor chip and the pad structure 316 a is provided on a secondsemiconductor chip which is different from the first semiconductor chip,the pad structures 311 a and 316 a can be used for communicating asignal through an interface between the first semiconductor chip and thesecond semiconductor chip (e.g., a bus connecting the firstsemiconductor chip and the second semiconductor chip). Especially whenthe interface is a high speed interface, the structure according to thepresent invention is suitable for the pad structures 311 a and 316 a.

[0187] Hereinafter, an effect of the present invention of reducing powerloss will be specifically described in comparison with the conventionalart.

[0188] Table 1 summarizes the effect of the present invention ofreducing power loss. In Table 1, “C_(p)” in column 1 represents a valueof the parasitic capacitance C_(p), “R_(p)” in column 2 represents avalue of the parasitic resistance R_(p), and “power loss” in column 3represents a value of the power consumed by the semiconductor integratedcircuit. The “power loss” is represented by a relative value withrespect to the power lose of conventional art example 1 which is set as1 (reference value). TABLE 1 Power C_(p) (pF) R_(p) (Ω) lossConventional art example 1 1 100 1 Conventional art example 2 2 1.1 1/16Present invention example 1 1 64 4/5 Present invention example 2 1 7.31/10 Present invention example 3 1.04 4.0 1/17 Present invention example4 1.04 1.1 1/60

[0189] It is understood from Table 1 that the power loss of presentinvention examples 1 through 4 is reduced compared to that ofconventional art example 1. It is also understood that the power loss ofpresent invention examples 3 and 4 is reduced compared to that ofconventional art example 2. Conventional art example 2, althoughsignificantly reducing the power loss, has a disadvantage in that anincrease in the parasitic capacitance C_(p) reduces the cutoff frequencyf_(t) of the MOS transistor receiving a signal which is input to thebonding pad. Conventional art example 2 has a further disadvantage inthat, as a result of breakdown of the insulating layer caused by theforce applied at the time of bonding, two metal plates may beundesirably shortcircuited or one of the metal plates and the siliconsubstrate may be undesirably shortcircuited.

[0190] The specific structures of conventional art examples 1 and 2 andpresent invention examples 1 through 4 are as follows.

[0191] Conventional art example 1: semiconductor integrated circuitincluding a bonding pad and a semiconductor substrate facing the bondingpad through an insulating layer interposed therebetween (see FIG. 22)

[0192] Conventional art example 2: semiconductor integrated circuitdescribed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 7, JULY1996, page 886, FIG. 10

[0193] Present invention example 1: semiconductor integrated circuit inthe first example according to the present invention (conductive layer:frame-shaped, without low resistance layer)

[0194] Present invention example 2: semiconductor integrated circuit inthe second example according to the present invention (conductive layer:frame-shaped, with low resistance layer)

[0195] Present invention example 3: semiconductor integrated circuit inthe third example according to the present invention (conductive layer:5×5 mesh type, without low resistance layer)

[0196] Present invention example 4: semiconductor integrated circuit inthe third example according to the present invention (conductive layer:5×5 mesh type, with low resistance layer)

[0197] The conditions by which the results shown in Table 1 are obtainedare as follows.

[0198] *Distance D_(BS) between the bonding pad and the semiconductorsubstrate: 2d

[0199] *Distance D_(BC) between the bonding pad and the conductivelayer: d (i.e., D_(BC)=1/2D_(BS))

[0200] *Capacitance between the bonding pad and the semiconductorsubstrate: 0.1 fF/μm² (i.e., capacitance between the bonding pad and theconductive layer: 0.2 fF/μm²)

[0201] *Sheet resistance ρ of the semiconductor substrate: 1000 Ω(except that ρ=50 Ω for present invention examples 2 and 4)

[0202] *Size of bonding pad: 100 μm×100 μm

[0203] *5×5 mesh type conductive layer: see FIG. 19; width of theconductive layer=0.5 μm (parasitic capacitance C_(p) is calculated inaccordance with the following expression)

C _(p)=0.1×(100×100−100×0.5×8)+0.2×100×0.5×8=1.04 pF

INDUSTRIAL APPLICABILITY

[0204] According to a semiconductor integrated circuit of the presentinvention, the parasitic resistance R_(p) can be reduced withoutsubstantially increasing the parasitic capacitance C_(p). Thus, thepower lose and noise generation caused by the parasitic element in thebonding pad can be reduced.

[0205] The semiconductor integrated circuit according to the presentinvention is applicable for a pad structure used in a receiving sectionof a communication system for receiving a signal. Thus, the power lossand noise generation caused when the signal is received can be reduced.The semiconductor integrated circuit according to the present inventionis applicable for a pad structure used in a transmitting section of acommunication system for transmitting a signal. Thus, the power loss andnoise generation caused when the signal is transmitted can be reduced.

[0206] Especially, the semiconductor integrated circuit according to thepresent invention is suitable for a pad structure used for transmittingor receiving a signal having a high frequency (e.g., 100 MHz or more).

1. (Amended) A semiconductor integrated circuit, comprising: a bondingpad; and a semiconductor substrate electrically insulated from thebonding pad, wherein: the semiconductor substrate has a first region anda second region; the first region is defined in a region facing thebonding pad; and the second region is defined as surrounding at least apart of the first region and not surrounding the first region in athickness direction of the semiconductor substrate, and the secondregion of the semiconductor substrate is set substantially at anequipotential.
 2. A semiconductor integrated circuit according to claim1, wherein the setting means includes: voltage supply means forsupplying a prescribed voltage; and connecting means for electricallyconnecting the voltage supply means to the second region of thesemiconductor substrate.
 3. A semiconductor integrated circuit accordingto claim 2, wherein the connecting means includes a conductive sectionelectrically connected to the voltage supply means and a plurality ofcontact portions discretely formed, and the plurality of contactportions each electrically connect the conductive section to the secondregion of the semiconductor substrate.
 4. A semiconductor integratedcircuit according to claim 3, wherein a shape of the second region ofthe semiconductor substrate is determined by a shape of the conductivesection.
 5. A semiconductor integrated circuit according to claim 3,wherein the conductive section has a shape substantially surrounding thefirst region of the semiconductor substrate.
 6. A semiconductorintegrated circuit according to claim 3, wherein the conductive sectionhas a plurality of basic cells arranged in an array.
 7. A semiconductorintegrated circuit according to claim 2, wherein the connecting meansincludes a conductive section electrically connected to the voltagesupply means and a contact portion continuously formed, and the contactportion electrically connects the conductive section to the secondregion of the semiconductor substrate.
 8. A semiconductor integratedcircuit according to claim 1, wherein the second region of thesemiconductor substrate is located outside the first region of thesemiconductor substrate.
 9. A semiconductor integrated circuit accordingto claim 1, wherein the second region of the semiconductor substrate islocated inside the first region of the semiconductor substrate.
 10. Asemiconductor integrated circuit according to any one of claims 1, 5 and8, further comprising a low resistance layer formed in at least a partof the first region of the semiconductor substrate.
 11. A semiconductorintegrated circuit according to claim 1, wherein the equipotential is aground potential.
 12. (Amended) A system, comprising: a transmitting andreceiving section for transmitting or receiving a signal; and aprocessing section for processing the signal to be transmitted or thesignal received, the transmitting and receiving section including a padstructure including a bonding pad; and a semiconductor substrateelectrically insulated from the bonding pad, wherein: the semiconductorsubstrate has a first region and a second region; the first region isdefined in a region facing the bonding pad; and the second region isdefined as surrounding at least a part of the first region and notsurrounding the first region in a thickness direction of thesemiconductor substrate, and the second region of the semiconductorsubstrate is set substantially at an equipotential.
 13. A systemaccording to claim 12, wherein the transmitting and receiving sectiontransmits or receives the signal through an antenna.
 14. A systemaccording to claim 12, wherein the transmitting and receiving sectiontransmits or receives the signal through an interface for connectingdifferent semiconductor chips.
 15. A system according to claim 12,wherein the signal has a frequency of 100 MHz or more.
 16. A systemaccording to claim 12, wherein the transmitting and receiving sectionand the processing section are formed on a single semiconductor chip.17. A system according to claim 12, wherein the transmitting andreceiving section transmits and receives the signal.